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this product incorporates superflash ? technology licensed from sst. ? motorola, inc., 2002 MC68HC908QY4SM/d rev. 0.1, 12/2002 mc68hc908qy4, mc68hc908qt4, mc68hc908qy2, mc68hc908qt2, mc68hc908qy1, mc68hc908qt1 data sheet summary introduction this document provides an overview of the mc68hc908qy4, mc68hc908qt4, mc68hc908qy2, mc68hc908qt2, mc68hc908qy1, and mc68hc908qt1 devices. for complete details refer to the mc68hc908qy4 data sheet (motorola document order number mc68hc908qy4/d). general description the mc68hc908qy4 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroll er units (mcus). the m68hc08 family is a complex instruction set computer (cisc) with a von neumann architecture. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are availabl e with a variety of modules, memory sizes and types, and package types. table 1. mc order numbers mc order number adc flash memory package mc68hc908qy1 ? 1536 bytes 16-pins pdip, soic, and tssop mc68hc908qy2 yes 1536 bytes mc68hc908qy4 yes 4096 bytes mc68hc908qt1 ? 1536 bytes 8-pins pdip, soic, and dfn mc68hc908qt2 yes 1536 bytes mc68hc908qt4 yes 4096 bytes temperature and package designators: c = ?40c to +85c v = ?40c to +105c (available for v dd = 5 v only) m = ?40c to +125c (available for v dd = 5 v only) p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) dt = thin shrink small outline package (tssop) fq = dual flat no lead (dfn)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 2 features motorola features features include: high-performance m68hc08 cpu core fully upward-compatible objec t code with m68hc05 family 5-v and 3-v operating voltages (v dd ) 8-mhz internal bus operation at 5 v, 4-mhz at 3 v trimmable internal oscillator ? 3.2 mhz internal bus operation ? 8-bit trim capability, 5% trimmed auto wakeup from stop capability configuration (config) register for mcu configuration options, including low-voltage inhibit (lvi) trip point in-system flash programming flash security (1) on-chip in-application programmable flash memory (with internal program/erase voltage generation) ? mc68hc908qy4 and mc68hc908qt4 ? 4096 bytes ? mc68hc908qy2, mc68hc908qy1, mc68hc908qt2, and mc68hc908qt1 ? 1536 bytes 128 bytes of on-chip random-access memory (ram) 2-channel, 16-bit timer interface module (tim) 4-channel, 8-bit analog-to-digital converter (adc) on mc68hc908qy2, mc68hc908qy4, mc68hc908qt2, and mc68hc908qt4 5 or 13 bidirectional input/output (i/o) lines and one input only: ? high current sink/source capability on all port pins ? selectable pullups on all ports, selectable on an individual bit basis 6-bit keyboard interrupt with wakeup feature (kbi) low-voltage inhibit (lvi) module featur es software selectable trip point in config register 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficul t for unauthorized users.
MC68HC908QY4SM/d mcu block diagram mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola mcu block diagram 3 system protection features: ? computer operating properly (cop) watchdog ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset external asynchronous interrupt pin with internal pullup (irq ) shared with general-purpose input pin master asynchronous reset pin (rst ) shared with general-purpose i/o pin power-on reset internal pullups on irq and rst to reduce external components memory mapped i/o registers power saving stop and wait modes mc68hc908qy4, mc68hc908qy2, and mc68hc908qy1 are available in these packages: ? 16-pin plastic dual in-line package (pdip) ? 16-pin small outline integrated circuit (soic) package ? 16-pin thin shrink small outline package (tssop) mc68hc908qt4, mc68hc908qt2, and mc68hc908qt1 are available in these packages: ? 8-pin pdip ? 8-pin soic ? 8-pin dual flat no lead (dfn) mcu block diagram see figure 1 . memory the central processor unit (cpu08) can a ddress 64 kbytes of memory space. the memory map is shown in figure 3 . addresses $0000?$003f, shown in figure 4 , contain most of the control, status, and data registers. the vector addresses are shown in table 3 .
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 4 memory motorola figure 1. block diagram mc68hc908qy4 and mc68hc908qt4: 4096 bytes mc68hc908qy2, mc68hc908qy1, mc68hc908qt2, and mc68hc908qt1: 1536 bytes user flash rst , irq : pins have internal (about 30k ohms) pull up pta[0:5]: high current sink and source capability pta[0:5]: pins have programmabl e keyboard interrupt and pull up ptb[0:7]: not available on 8-pin devices ? mc68hc908qt1, mc68hc908qt2, and mc68hc908qt4 condition code register v 1 1 i n z c h index register cpu control stack pointer alu 68hc08 cpu accumulator program counter cpu registers 128 bytes ram v dd v ss 16-bit timer module cop module power-on reset module break module single interrupt module system integration module clock generator ptb ddrb monitor rom 8-bit adc pta ddra ptb[0:7] power supply pta0/ad0/tch0/kbi0 pta1/ad1/tch1/kbi1 pta2/irq /kbi2 pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5
MC68HC908QY4SM/d pin assignments mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola pin assignments 5 pin assignments figure 2. mcu pin assignments 1 2 3 4 5 6 7 8 ptb0 ptb2 ptb3 ptb4 v ss ptb6 ptb7 ptb1 8-pin assignment mc68hc908qt1 pdip/soic 16-pin assignment mc68hc908qy1 pdip/soic v ss v dd pta5/osc1/kbi5 1 2 3 4 8 7 6 5 pta4/osc2/kbi4 pta3/rst /kbi3 pta1/tch1/kbi1 pta0/tch0/kbi0 pta2/irq /kbi2 v dd pta1/tch1/kbi1 ptb5 pta2/irq /kbi2 pta0/tch0/kbi0 pta5/osc1/kbi5 pta4/osc2/kbi4 pta3/rst /kbi3 1 2 3 4 5 6 7 16 15 14 13 12 11 10 8 ptb2 ptb3 ptb4 ptb6 ptb7 16-pin assignment mc68hc908qy1 tssop pta1/tch1/kbi1 ptb5 pta2/irq /kbi2 pta5/osc1/kbi5 pta4/osc2/kbi4 pta3/rst /kbi3 pta0/tch0/kbi0 ptb1 ptb0 v ss v dd 8-pin assignment mc68hc908qt2 and mc68hc908qt4 pdip/soic v ss v dd pta5/osc1/ad3/kbi5 1 2 3 4 8 7 6 5 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 pta1/ad1/tch1/kbi1 pta0/ad0/tch0/kbi0 pta2/irq /kbi2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ptb0 ptb2 ptb3 ptb4 v ss ptb6 ptb7 ptb1 16-pin assignment mc68hc908qy2 and mc68hc908qy4 pdip/soic v dd pta1/ad1/tch1/kbi1 ptb5 pta2/irq /kbi2 pta0/ad0/tch0/kbi0 pta5/osc1/ad3/kbi5 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 1 2 3 4 5 6 7 16 15 14 13 12 11 10 9 8 ptb2 ptb3 ptb4 ptb6 ptb7 16-pin assignment mc68hc908qy2 and mc68hc908qy4 tssop pta1/ad1/tch1/kbi1 ptb5 pta2/irq /kbi2 pta5/osc1/ad3/kbi5 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 pta0/ad0/tch0/kbi0 ptb1 ptb0 v ss v dd 16 15 14 13 12 11 10 9 9 pta0/tch0/kbi0 v ss v dd pta5/osc1/kb15 8-pin assignment mc68hc908qt1 dfn 8-pin assignment mc68hc908qt2 and mc68hc908qt4 dfn 1 2 3 4 8 7 6 5 pta1/tch1/kbi1 pta3/rst /kbi3 pta2/irq /kbi2 pta4/osc2/kbi4 pta0/ad0/tch0/kbi0 v ss v dd pta5//osc1/ad3/kb15 1 2 3 4 8 7 6 5 pta1/ad1/tch1/kbi1 pta3/rst /kbi3 pta2/irq /kbi2 pta4/osc2/ad2/kbi4
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 6 pin functions motorola pin functions table 2 provides a description of the pin functions. table 2. pin functions pin name description input/output v dd power supply power v ss power supply ground power pta0 pta0 ? general purpose i/o port input/output ad0 ? a/d channel 0 input input tch0 ? timer channel 0 i/o input/output kbi0 ? keyboard interrupt input 0 input pta1 pta1 ? general purpose i/o port input/output ad1 ? a/d channel 1 input input tch1 ? timer channel 1 i/o input/output kbi1 ? keyboard interrupt input 1 input pta2 pta2 ? general purpose input-only port input irq ? external interrupt with programmable pullup and schmitt trigger input input kbi2 ? keyboard interrupt input 2 input pta3 pta3 ? general purpose i/o port input/output rst ? reset input, active low with internal pullup and schmitt trigger input kbi3 ? keyboard interrupt input 3 input pta4 pta4 ? general purpose i/o port input/output osc2 ? xtal oscillator ou tput (xtal option only) rc or internal oscillator output (osc2en = 1 in ptapue register) output output ad2 ? a/d channel 2 input input kbi4 ? keyboard interrupt input 4 input pta5 pta5 ? general purpose i/o port input/output osc1 ?xtal, rc, or external oscillator input input ad3 ? a/d channel 3 input input kbi5 ? keyboard interrupt input 5 input ptb[0:7] (1) 8 general-purpose i/o ports. input/output 1. the ptb pins ar e not available on the 8-pin packages.
MC68HC908QY4SM/d pin functions mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola pin functions 7 $0000 ? % note 1. attempts to execute code from addresses in this range will generate an illegal address reset. $0040 ? 0? ?? ? ? ?? 0? ?? ? ?? 0? ? ?? ?? ? ? ? ? ? 0 ?;?; ?;? ? 0 ? 0 0 ?0? 0? 0 0 0 0 0 0 ? ? ? 0 ? ? figure 3. memory map
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 8 pin functions motorola addr. register bit 7654321bit 0 $0000 pta r awul pta5 pta4 pta3 pta2 pta1 pta0 $0001 ptb ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 $0002 unimplemented $0003 unimplemented $0004 ddra r r ddra5 ddra4 ddra3 0 ddra1 ddra0 $0006 ddrb ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 $0007? $000a unimplemented unimplemented $000b ptapue osc2en 0 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 $000c ptbpue ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 $000d? $0019 unimplemented unimplemented $001a kbscr 0 0 0 0 keyf ackk imaskk modek $001b kbier 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 $001c unimplemented $001d intscr 0 0 0 0 irqf1 ack1 imask1 mode1 $001e config2 irqpud irqen oscopt1 oscopt0 rsten $001f config1 coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd $0020 tsc tof toie tstop trst 0 ps2 ps1 ps0 $0021 tcnth bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 $0022 tcntl bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0 $0023 tmodh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 $0024 tmodlbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 $0025 tsc0 ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max $0026 tch0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 $0027 tch0l bit 7 bit 6 bit 5 bit 4bit 3bit 2bit 1bit 0 $0028 tsc1 ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max $0029 tch1h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 $002a tch1l bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $002b? $0035 unimplemented unimplemented $0036 oscstat ecgon ecgst $0037 unimplemented $0038 osctrim trim7 trim6 trim 5 trim4 trim3 trim2 trim1 trim0 $0039? $003b unimplemented unimplemented $003c adscr coco aien adco ch4 ch3 ch2 ch1 ch0 $003d unimplemented $003e adrad7ad6ad5ad4ad3ad2ad1ad0 $003f adiclk adiv2 adiv1 adiv0 0 0 0 0 0 = unimplemented or reserved figure 4. control, status, and data registers (sheet 1 of 2)
MC68HC908QY4SM/d pin functions mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola pin functions 9 . $fe00 bsr sbsw $fe01 srsr por pin cop ilop ilad modrst lvi 0 $fe02 brkar0000000bdcop $fe03 bfcr bcfe $fe04 int1 0 if5 if4 if3 0 if1 0 0 $fe05 int2if140000000 $fe06 int30000000if15 $fe07 reserved $fe08 flcr 0 0 0 0 hven mass erase pgm $fe09 brkh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 $fe0a brkl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $fe0b brkscrbrkebrka000000 $fe0c lvisrlviout000000 $fe0d? $fe0f reserved for flash test reserved for flash test $ffbe flbpr bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 $ffbf reserved $ffc0 trimloc non-volatile trim adjustment value $ffc1 reserved $ffff copctl write any value to reset cop watchdog addr. register bit 7654321bit 0 = unimplemented or reserved figure 4. control, status, and data registers (sheet 2 of 2) table 3. vector addresses vector priority vector address vector lowest if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 through if6 ? not used if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if2 ? not used if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 10 flash module motorola flash module the flash memory consists of an array of 4096 or 1536 bytes with an additional 80 bytes for user vectors and miscellaneous. the minimum size of flash memory that can be erased is 64 bytes; and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). program and erase operations are fa cilitated through control bits in the flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $ee00?$fdff; user memory, 4096 bytes: mc68hc908qy4 and mc68hc908qt4 $f800?$fdff; user memory, 1536 bytes: mc68hc908qy2, mc68hc908qt2, mc68hc908qy1 and mc68hc908qt1 $ffb0?$ffff; user interrupt vectors etc., 80 bytes. note: an erased bit reads as logic 1 and a programmed bit reads as logic 0. a security feature prevents unauthorized viewing of the flash contents. flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit 1 = high voltage enabled to array and charge pump on mass ? mass erase control bit 1 = mass erase operation selected erase ? erase control bit 1 = erase operation selected pgm ? program control bit 1 = program operation selected flash page erase operation use the following procedure to erase a page of flash memory. a page consists of 64 consecutive bytes st arting from addresses $xx00, $xx40, $xx80, or $xxc0. the 80-byte user interrupt vectors area includes two pages ($ffb0?$ffbf and $ffc0?$ffff). any flash memory page can be erased alone. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register ($ffbe). $fe08bit 7654321bit 0 0000hvenmasserasepgm reset:00000000 figure 5. flash control register (flcr)
MC68HC908QY4SM/d flash module mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola flash module 11 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase and mass bits. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. in applications that need up to 10,000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specificat ion. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a lower minimum erase time. flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addr esses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0, or $xxe0. us e the following step- by-step procedure to program a row of flash memory. note: only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register ($ffbe). 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 6 and 7 until desired bytes within the row are programmed. 10. clear the pgm bit (1) . 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum.
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 12 flash module motorola 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. flash block protect register the flash block protect register is implemented as a byte within the flash memory, and therefore it is programmed using a flash memory byte- programming operation. the value in this register determines the starting address of the protected range within the flash memory. the flash is protected from this address to the end of flash memory at $ffff. bpr[7:0] ? flash protection register bits [7:0] figure 7. flash block protect start address $ffbebit 7654321bit 0 bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 reset: unaffected by reset. initial value from factory is all 1?s. figure 6. flash block protect register (flbpr) table 4. examples of protect start address bpr[7:0] start of address of protect range $00?$b8 the entire flash memory is protected. $b9 ( 1011 1001 ) $ee40 (11 10 1110 01 00 0000) $ba ( 1011 1010 ) $ee80 (11 10 1110 10 00 0000) $bb ( 1011 1011 ) $eec0 (11 10 1110 11 00 0000) $bc ( 1011 1100 ) $ef00 (11 10 1111 00 00 0000) and so on... $de ( 1101 1110 ) $f780 (11 11 0111 10 00 0000) $df ( 1101 1111 )$f7c0 (11 11 0111 11 00 0000) $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) flbpr, osctrim, and vectors are protected $ff the entire flash memory is not protected. 0 0 0 0 0 1 1 flbpr value start address of 16-bit memory address protected flash block 0
MC68HC908QY4SM/d configuration registers (config1, config2) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola configuration registers (config1, config2) 13 configuration registers (config1, config2) the configuration registers are used to initialize various options. the configuration registers can each be writt en once after each reset. most of the configuration register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu) it is recommended that these registers be written immediately after reset. the configuration registers are located at $001e and $001f, and may be read at anytime. irqpud ? irq pin pullup disable control bit 0 = internal pullup is connected between irq pin and v dd (if irqen = 1) irqen ? irq pin function selection bit 1 = pta2/irq /kbi2 pin configured for irq function 0 = pin configured for pta2 or kbi2 function oscopt1:oscopt0 ? selection bits for oscillator option (0:0) internal oscillator (0:1) external oscillator (1:0) external rc oscillator (1:1) external xtal oscillator rsten ? rst pin function selection 1 = pta2/rst /kbi3 pin configured for reset function 0 = pin configured for pta3 or kbi3 function note: the rsten bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. coprs (out of stop mode) ? cop reset period selection bit 1 = cop reset short cycle = (2 13 ?2 4 ) x busclkx4 0 = cop reset long cycle = (2 18 ?2 4 ) x busclkx4 to prevent a reset due to a cop watchdog timeout, write any value to copctl ($ffff) before the cop timer reaches the selected timeout. $001e bit 7 6 5 4 3 2 1 bit 0 irqpud irqen r oscopt1 oscopt0 r r rsten reset: por: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u 0 r = reserved u = unaffected figure 8 configuration register 2 (config2) $001f bit 7 6 5 4 3 2 1 bit 0 coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd reset: por: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u = unaffected figure 9 configuration register 1 (config1)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 14 lvi status register motorola coprs (in stop mode) ? auto wakeup period selection bit 1 = auto wakeup short cycle = approximately 16 ms 0 = auto wakeup long cycle = approximately 650 ms lvistop ? lvi enable in stop mode bit 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit 1 = lvi module power disabled lvi5or3 ? lvi 5-v or 3-v operating mode bit 1 = lvi operates in 5-v mode 0 = lvi operates in 3-v mode note: the lvi5or3 bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit 1 = stop mode recovery after 32 busclkx4 cycles 0 = stop mode recovery after 4096 busclkx4 cycles note: exiting stop mode by an lvi reset will result in the long stop recovery. stop ? stop instruction enable bit 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit 1 = cop module disabled (does not force resets) lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level while lvi resets have been disabled . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . $fe0cbit 7654321bit 0 lviout000000r reset:00000000 r= reserved figure 10. lvi status register (lvisr)
MC68HC908QY4SM/d irq status and control register mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola irq status and control register 15 irq status and control register irqf1 ? irq flag this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending ack1 ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack1 always reads as logic 0. imask1 ? irq interrupt mask bit 1 = irq interrupt requests disabled mode1 ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only sim reset stat us register this register contains seven flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit pin ? external reset bit 1 = last reset caused by external reset pin (rst ) cop ? computer operating properly reset bit 1 = last reset caused by cop timeout ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode $001d bit 7 654321bit 0 0000irqf1ack1imask1mode1 reset:00000000 figure 11. irq status and control register (intscr) $fe01bit 7654321bit 0 por pin cop ilop ilad modrst lvi 0 por:10000000 figure 12. sim reset status register (srsr)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 16 interrupt status registers (int1, int2, int3) motorola ilad ? illegal address reset bit (ill egal attempt to fetch an opcode from an unimplemented address) 1 = last reset caused by an opcode fetch from an illegal address modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while pta2/irq = v dd lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit interrupt status register s (int1, int2, int3) these three registers include status flags which indicate which interrupt sources currently have pending requests. see table 3 . ifxx ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown below the corresponding ifxx bit. 1 = interrupt request pending 0 = no interrupt request present $fe04bit 7654321bit 0 0if5if4if30if10 0 reset:00000000 source: tof tch1 tch0 irq figure 13. interrupt status register 1 (int1) $fe05bit 7654321bit 0 if140000000 reset:00000000 source: kbi figure 14. interrupt status register 2 (int2) $fe06bit 7654321bit 0 0000000if15 reset:00000000 source: adc figure 15. interrupt status register 3 (int3)
MC68HC908QY4SM/d central processor unit (cpu) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola central processor unit (cpu) 17 central processor unit (cpu) figure 16 shows the five cpu registers. cpu regist ers are not part of the memory map. figure 16. cpu registers accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 18 instruction set summary motorola instruction set summary table 5 provides a summary of t he m68hc08 instruction set. table 5. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) !! ? !!! imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) !! ? !!! imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? !! ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ! ?? !!! dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ! ?? !!! dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 c b0 b7 0 b0 b7 c
MC68HC908QY4SM/d instruction set summary mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola instruction set summary 19 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? !! ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ! dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 table 5. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 20 instruction set summary motorola brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ! dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ! ?? !!! imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? !! 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ! ?? !!! imm dir 65 75 ii ii+1 dd 3 4 table 5. instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
MC68HC908QY4SM/d instruction set summary mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola instruction set summary 21 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ! ?? !!! imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? !!! inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ! ?? !! ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? !! inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? !! ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ! ?? !! ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? !! ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 5. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 22 instruction set summary motorola ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? !! ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? !! ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ! ?? !!! dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ! ??0 !! dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? !! ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ! ?? !!! dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? !! ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp ) ? 1 ??????inh 87 2 pshh push h onto stack push (h) ; sp (sp ) ? 1 ??????inh 8b 2 pshx push x onto stack push (x) ; sp (sp ) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 table 5. instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
MC68HC908QY4SM/d instruction set summary mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola instruction set summary 23 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ! ?? !!! dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ! ?? !!! dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) !!!!!! inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ! ?? !!! imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? !! ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? !! ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? !! ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ! ?? !!! imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 5. instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 24 instruction set summary motorola swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) !!!!!! inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? !! ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ! set or cleared n negative bit ? not affected table 5. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
MC68HC908QY4SM/d oscillator module (osc) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola oscillator module (osc) 25 oscillator module (osc) the oscillator has these four clock source options available: 1. internal oscillator: an internally generated, fixed frequency clock, trimmable to 5% in steps of approximately 0.2%. this is the default option out of reset. 2. external oscillator: an external clock that can be driven directly into osc1. 3. external rc: a built-in oscillator m odule (rc oscillator) that requires an external r connection only on one pin. the capacitor will be internal to the chip. 4. external crystal: a built-in oscill ator module (xtal oscillator) that requires an external crystal or ceramic-resonator on two pins. internal to external clock switching when external clock source (external os c, rc, or xtal) is desired, the user must perform the following steps: 1. for external crystal circuits only, oscopt[1:0] = 1:1: to help precharge an external crystal oscillator, set pta4 (osc2) as an output and drive high for several cycles. before writing oscopt[1:0], the crystal will see a sharp falling edge at startup. 2. set config2 bits osco pt[1:0] according to table 7 . the oscillator module control logic will then set os c1 as an external clock input and, if the external crystal option is selected, osc2 will also be set as the clock output. 3. create a software delay to wait the stabilization time needed for the selected clock source (crystal, re sonator, rc) as recommended by the component manufacturer. a good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-mhz crystal, wait approximately 1 msec. 4. after this delay has elapsed, the ecgon bit in the osc status register (oscstat) should be set by the user software. 5. after ecgon set is detected, the osc module checks for oscillator activity by waiting two external clock rising edges. 6. the osc module than switches to the external clock. logic provides a glitch free transition. 7. the osc module sets the ecgst bit in the oscstat register and then stops the internal oscillator. note: once transition to the external clock is d one, the internal oscillator will only be reactivated with reset. clock does not switch back to internal if external clock stops.
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 26 oscillator module (osc) motorola figure 17. xtal oscillator external connections figure 18. rc oscillator external connections c 1 c 2 simoscen xtalclk r b x 1 r s (1) mcu from sim pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 2 busclkx2 busclkx4 to sim to sim note 1. r s can be zero (shorted) when used with higher-frequency crystals. refer to crystal manufacturer?s data. mcu r ext simoscen pta5/osc1/ad3/kbi5 external rc oscillator en rcclk 2 busclkx2 busclkx4 to sim from sim v dd pta4 i/o 1 0 pta4 osc2en pta4/osc2/ad3/kbi4 to sim 0 1 intclk oscrcopt
MC68HC908QY4SM/d oscillator module (osc) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola oscillator module (osc) 27 oscillator status register the oscillator status register (oscstat ) contains the bits for switching from internal to external clock sources ecgon ? external clock generator on bit 1 = external clock generator enabled ecgst ? external clock status bit 1 = an external clock source engaged oscillator trim register (osctrim) trim7?trim0 ? internal osc illator trim factor bits these read/write bits change the size of the internal capacitor used by the internal oscillator. by testing t he frequency of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed period (the period for trim = $80). the trimmed frequency is guaranteed not to vary by more than 5% over the full specified range of temperature and voltage. the reset value is $80 which sets the frequency to 3.2 mhz 25% (bus rate). a trim adjustment factor can be programmed into flash memory at trimloc ($ffc0). during the applicati on initialization routine, this value can be read from trimloc and be stored to osctrim ($0038) to fine tune the internal oscillator frequency. $0036 bit 7 654321bit 0 rrrrrr ecgon ecgst reset:000 00 000 r=reserved figure 19. oscillator status register (oscstat) $0038 bit 7 654321bit 0 trim7 trim6 trim5 trim4 trim3 trim2 trim71 trim0 reset:10000000 figure 20. oscillator trim register (osctrim)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 28 timer interface module (tim) motorola timer interface module (tim) features of the tim include the following: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation optional toggle of any channel pin on overflow tim counter stop and reset bits figure 21. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic ?;;;;?;; toggle
MC68HC908QY4SM/d timer interface module (tim) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola timer interface module (tim) 29 pwm initialization recommended initialization procedure for unbuffered or buffered pwm signals. 1. in tsc: a. stop the tim counter by setting tstop. b. reset the tim counter and prescaler by setting trst. 2. write tmodh:tmodl to set the required pwm period. 3. write tchxh:tchxl to set the required pulse width. 4. write tim channel x status and control register (tscx) to select the desired function: a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 7 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 7 . 5. clear tstop in the tim status control register (tsc). tim status and control register tof ? tim overflow flag bit tof is set when the tim counter reac hes the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. 1 = tim counter has reached modulo value toie ? tim overflow interrupt enable bit 1 = tim overflow interrupts enabled tstop ? tim stop bit 1 = tim counter stopped trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. trst is cleared automatically after the tim counter is reset and always reads as logic 0. 1 = prescaler and tim counter cleared note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. $0020 bit 7 654321bit 0 tof toie tstop trst 0 ps2 ps1 ps0 reset:00100000 figure 22. tim status and control register (tsc)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 30 timer interface module (tim) motorola ps[2:0] ? prescaler select bits tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. tim counter modulo registers when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. table 6. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 reserved tcnth $0021 bit 7 654321bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset:00000000 tcntl $0022 bit 7 654321bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset:00000000 figure 23. tim counter registers (tcnth:tcntl) tmodh $0023 bit 7 654321bit 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 reset:11111111 tmodl $0024 bit 7 654321bit 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset:11111111 figure 24. tim counter modulo registers (tmodh:tmodl)
MC68HC908QY4SM/d timer interface module (tim) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola timer interface module (tim) 31 tim channel status and control registers chxf ? channel x flag bit when channel x is an input capture channel, chxf is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. clear chxf by reading the tim channel x status and control register with chxf set and then writing a logic 0 to chxf. 1 = input capture or output compare on channel x chxie ? channel x interrupt enable bit 1 = channel x cpu interrupt requests enabled msxb, msxa, elsxb, and elsxa tovx ? toggle-on-overflow bit 1 = channel x pin toggles on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. tsc0 $0025 bit 7 654321bit 0 ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max reset:00000000 tsc1 $0028 bit 7 654321bit 0 ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max reset:00000000 figure 25. tim channel status and control registers (tsc0, tsc1) table 7. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 32 timer interface module (tim) motorola chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setti ng the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 26. chxmax latency tim channel registers in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) i nhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tch0h $0026 bit 7 654321bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset: indeterminate after reset tch0l $0027 bit 7 654321bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset: indeterminate after reset tch1h $0029 bit 7 654321bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset: indeterminate after reset tch1l $002a bit 7 654321bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset: indeterminate after reset figure 27. tim channel registers (tch0h:l, tch1h:l)
MC68HC908QY4SM/d analog-to-digital converter (adc) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola analog-to-digit al converter (adc) 33 analog-to-digital converter (adc) the adc is an 8-bit, 4-channel analog-to-digital converter. the adc module is only available on the mc68hc90 8qy2, mc68hc908qt2, mc68hc908qy4, and mc68hc908qt4. features of the adc module include: 4 channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock figure 28. adc block diagram conversion time internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock ch[4:0] adc data register adiv[2:0] aien coco (1 of 4 channels) a/d pin inputs ad[3:0] 16 adc clock cycles conversion time = adc clock frequency number of bus cycles = conversion time bus frequency
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 34 analog-to-digital converter (adc) motorola adc status and control register coco ? conversions complete bit when the aien bit is a logic 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever adscr is written or whenever the adr is read. when the aien bit is a logic 1 (cpu interrupt enabled), coco will always be logic 0 when read. 1 = conversion completed (aien = 0) aien ? adc interrupt enable bit 1 = adc interrupt enabled adco ? adc continuous conversion bit 1 = continuous adc conversion 0 = single adc conversion ch[4:0] ? adc channel select bits note: startup from the adc power off state requires one conversion cycle to stabilize. $003c bit 7 654321bit 0 coco aien adco ch4 ch3 ch2 ch1 ch0 reset:00011111 figure 29. adc status and control register (adscr) table 8. mux channel select ch4 ch3 ch2 ch1 ch0 adc channel input select 00000 ad0 pta0 00001 ad1 pta1 00010 ad2 pta4 00011 ad3 pta5 0 1 0 1 1 0 0 1 0 0 ? ? ? unused (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown. 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1? v dda (2) 2. the voltage levels supplied from internal refere nce nodes, as specified in the table, are used to verify the operation of the adc converter both in production test and for user applications. 11 1 1 0? v ssa (2) 11 1 1 1? adc power off
MC68HC908QY4SM/d input/output (i/o) ports mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola input/output (i/o) ports 35 adc data register this register is updated each time an adc conversion completes. adc input clock register adiv2?adiv0 ? adc clock prescaler bits input/output (i/o) ports port a port a is an 6-bit special function port that shares all six of its pins with the keyboard interrupt (kbi) module. each port a pin also has a software configurable pullup device if the corre sponding port pin is configured as a general-purpose input port, a kbi input, or the irq input. pta3 has a fixed pullup device when configured as rst . note: pta2 is input only. port a data register $003e bit 7 654321bit 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 reset: indeterminate after reset figure 30. adc data register (adr) $03fbit 7654321bit 0 adiv2adiv1adiv000000 reset:00000000 figure 31. adc input clock register (adiclk) table 9. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 bus clock 1 0 0 1 bus clock 2 0 1 0 bus clock 4 0 1 1 bus clock 8 1 x x bus clock 16 x = don?t care $0000 bit 7 6 5 4 3 2 1 bit 0 r awulpta5pta4pta3pta2pta1pta0 reset: unaffected by reset additional functions: kbi5 ad3 osc1 kbi4 ad2 osc2 kbi3 rst kbi2 irq kbi1 ad1 tch1 kbi0 ad0 tch0 r= reserved figure 32. port a data register (pta)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 36 input/output (i/o) ports motorola pta[5:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a (pta2 is input only). reset has no effect on port a data. awul ? auto wakeup latch data bit this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally. data direction register a ddra[5:0] ? data direction register a bits 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input port a input pullup enable register osc2en ? enable clock output on osc2 pin this read/write bit configures the osc2 pin function as a reference frequency output when internal oscillator or rc oscillator option is selected. this bit has no effect for the xtal oscillator or external oscillator options. 1 = osc2 pin outputs the internal or rc oscillator clock (busclkx4) ptapue[5:0] ? port a input pullup enable bits 1 = corresponding port a pin configured to have internal pull if its ddra bit is set to 0 and no alternat e function such as kbi, irq , or timer controls the pin. $0004 bit 7 6 5 4 3 2 1 bit 0 r r ddra5 ddra4 ddra3 0 ddra1 ddra0 reset:00000000 r= reserved figure 33. data direction register a (ddra) $000bbit 7654321bit 0 osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue2 ptapue0 reset:00000000 figure 34. port a input pullup enable register (ptapue)
MC68HC908QY4SM/d input/output (i/o) ports mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola input/output (i/o) ports 37 port b port b is an 8-bit general purpose i/o port. port b is only available on the mc68hc908qy1, mc68hc908qy2, and mc68hc908qy4. port b data register ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. data direction register b ddrb[7:0] ? data direction register b bits 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input port b input pullup enable register ptbpue[7:0] ? port b input pullup enable bits these read/write bits are software pr ogrammable to enable pullup devices on port b pins 1 = corresponding port b pin configured to have internal pull if its ddrb bit is set to 0 $0001 bit 7 6 5 4 3 2 1 bit 0 ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 reset: unaffected by reset figure 35. port b data register (ptb) $0005 bit 7 6 5 4 3 2 1 bit 0 ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 reset:00000000 figure 36. data direction register b (ddrb) $000c bit 7 654321bit 0 ptbpue7 ptbpue6 ptbpue5 ptbpue4 pt bpue3 ptbpue2 ptbpue2 ptbpue0 reset:00000000 figure 37. port b input pullup enable register (ptbpue)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 38 keyboard interrupt module (kbi) motorola keyboard interrup t module (kbi) features of the keyboard interrupt module include: six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask pullup device if input pin is configured as a keyboard interrupt input programmable edge-only or edge and level interrupt sensitivity exit from low-power modes figure 38. keyboard interrupt block diagram kbie0 kbie5 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi5 kbi0 synchronizer keyf keyboard interrupt request to pullup enable awuireq (1) to pullup enable 1. for awugen logic refer to figure 41 .
MC68HC908QY4SM/d auto wakeup module (awu) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola auto wakeup module (awu) 39 keyboard status and control register keyf ? keyboard flag bit 1 = keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request on port a and auto wakeup logic. ackk always reads as logic 0. imaskk? keyboard interrupt mask bit 1 = keyboard interrupt requests masked (disabled) modek ? keyboard triggering sensitivity bit 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only keyboard interrupt enable register kbie5?kbie0 ? port a keyboard interrupt enable bits 1 = kbix pin enabled as keyboard interrupt pin note: awuie bit is not used in conjunction with the keyboard interrupt feature. to see a description of this bit, see auto wakeup module (awu) . auto wakeup module (awu) features of the auto wakeup module include: one internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit. exit from low-power stop mode without external signals. selectable timeout periods of 16 milliseconds or 512 milliseconds. dedicated low power internal oscillat or separate from the main system clock sources. $001a bit 7 654321bit 0 0000 keyf ackk imaskk modek reset:00000000 figure 39. keyboard status and control register (kbscr) $001b bit 7 654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 reset:00000000 figure 40. keyboard interrupt enable register (kbier)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 40 auto wakeup module (awu) motorola figure 41. auto wakeup interrupt request generation logic note: the typical values of the periodic wake-up request are (at room temperature): ? coprs = 0: 650 ms @ 5 v, 950 ms @ 3 v coprs = 1: 16 ms @ 5 v, 23 ms @ 3 v input/output registers the awu shares registers with the keyboard interrupt (kbi) module and the port a i/o module. the following i/o regi sters control and monitor operation of the awu: port a data register (pta) keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) port a data register d r v dd int rc osc en 32 khz clk rst overflow autowugen short coprs (from config1) 1 = div 2 9 0 = div 2 14 e reset ackk clear rst reset clk (cgmxclk) busclkx4 istop awuireq clrlogic reset awul to pta read, bit 6 q awuie to kbi interrupt logic (see figure 38 ) address: $0000 $0000 bit 7 654321bit 0 0 awul pta5 pta4 pta3 pta2 pta1 pta0 reset: 0 0 unaffected by reset figure 42. port a data register (pta)
MC68HC908QY4SM/d auto wakeup module (awu) mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola auto wakeup module (awu) 41 awul ? auto wake-up latch this is a read-only bit which has the value of the auto wake-up interrupt request latch. the wake-up request signal is generated internally. there is no pta6 port or any of the associated bits such as pta6 data direction or pullup bits. 1 = auto wake-up interrupt request is pending note: pta5?pta0 bits are not used in conjuction with the auto wake-up feature. to see a description of these bits, see port a data register . keyboard status and control register keyf ? keyboard flag bit 1 = keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request on port a and auto wakeup logic. ackk always reads as logic 0. imaskk? keyboard interrupt mask bit 1 = keyboard interrupt requests masked (disabled) note: modek is not used in conjuction with the auto wake-up feature. to see a description of this bit, see keyboard interrupt module (kbi) . keyboard interrupt enable register awuie ? auto wakeup interrupt enable bit this read/write bit enables the auto wake-up interrupt input to latch interrupt requests. reset clears awuie. 1 = auto wakeup enabled as interrupt input note: kbie5?kbie0 bits are not used in conjuction with the auto wake-up feature. to see a description of these bits, see keyboard interrupt module (kbi) . $001a bit 7 654321bit 0 0000 keyf ackk imaskk modek reset:00000000 figure 43. keyboard status and control register (kbscr) $001b bit 7 654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 reset:00000000 figure 44. keyboard interrupt enable register (kbier)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 42 break module motorola break module this section describes the breakpoint m odule which works in conjunction with third-party development software to allow development of debugging of application systems. break status and control register brke ? break enable bit this read/write bit enables breaks on break address register matches. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. 1 = break address match break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. $fe0bbit 7654321bit 0 brkebrka000000 reset:00000000 figure 45. break status and control register (brkscr) $fe09bit 7654321bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset:00000000 figure 46. break address register high (brkh) $fe0abit 7654321bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset:00000000 figure 47. break address register low (brkl)
MC68HC908QY4SM/d break module mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola break module 43 break auxiliary register the break auxiliary register (brkar) cont ains a bit that enables software to disable the cop while the mcu is in a state of break interrupt with monitor mode. bdcop ? break disable cop bit 1 = cop disabled during break interrupt break flag control register the break control register (bfcr) contai ns a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break break status register the break status register (bsr) is reserved for use in supporting third party emulation systems. $fe02bit 7654321bit 0 0000000bdcop reset:00000000 figure 48. break auxiliary register (brkar) $fe03bit 7654321bit 0 bcferrrrrrr reset: 0 r= reserved figure 49. break flag control register (bfcr) $fe00bit 7654321bit 0 rrrrrrsbswr reset: 0 r= reserved figure 50. break status register (bsr)
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 44 condensed electrical characteristics motorola condensed electrical characteristics for more detailed information refer to the mc68hc908qy4 data sheet (motorola document order number mc68hc908qy4/d). 5-volt dc electrical characteristics 5-volt control timing characteristic (1) symbol min typ (2) max unit v dd supply current run, f op = 4 mhz (3) wait (4) stop (5) , ?40c to 85c i dd ? ? ? 7 5 1 10 5.5 5 ma ma a por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi v dd + 2.5 ?9.1v pullup resistors (8) rst , irq , pta0?pta5, ptb0?ptb7 r pu 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 3.90 4.20 4.50 v low-voltage inhibit reset, trip rising voltage v tripr 4.00 4.30 4.60 v low-voltage inhibit reset/recover hysteresis v hys ? 100 ? mv 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurement s at midpoint of voltage range, 25c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inputs. measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. all ports configured as inputs. 5. all ports configured as inputs. all ports driven 0.2 v or less from rail. no dc loads. on the 8-pin versions, port b is conf igured as inputs with pullups enabled. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0 v. characteristic (1) symbol min max unit internal operating frequency (2) f op ?8mhz rst input pulse width low (3) t irl 750 ? ns 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. 2. some modules may require a minimum frequency greater than dc for proper operation; s ee appropriate table for this information. 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset.
MC68HC908QY4SM/d condensed electrical characteristics mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola condensed electr ical characteristics 45 5-volt oscillator characteristics figure 51. rc versus frequency (5 volts @ 25c) characteristic symbol min typ max unit internal oscillator frequency f intclk ?12.8?mhz crystal frequency, xtalclk f oscxclk 8?16mhz rc oscillator frequency, rcclk f rcclk 2?12mhz external clock reference frequency (1) f oscxclk dc ? 16 mhz 1. no more than 10% duty cycle deviation from 50%. 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ; 0 ?
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 46 condensed electrical characteristics motorola 3-volt dc electrical characteristics 3-volt control timing characteristic (1) symbol min typ (2) max unit v dd supply current run, f op = 2 mhz (3) wait, f op = 2 mhz (4) stop (5) ,?40c to 85c i dd ? ? ? 5 1 1 8 2.5 5 ma ma a por rearm voltage (6) v por 0 ? 100 mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi v dd + 2.5 ? v dd + 4.0 v pullup resistors (8) rst , irq , pta0?pta5, ptb0?ptb7 r pu 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 2.40 2.55 2.70 v low-voltage inhibit reset, trip rising voltage v tripr 2.50 2.65 2.80 v low-voltage inhibit reset/recover hysteresis v hys ?60?mv 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurement s at midpoint of voltage range, 25c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as in puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd . 5. all ports configured as inputs. all port s driven 0.2 v or less from rail. no dc loads. on the 8-pin versions, port b is conf igured as inputs with pullups enabled. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0 v characteristic (1) symbol min max unit internal operating frequency (2) f op ?4mhz rst input pulse width low (3) t irl 1.5 ? s 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. some modules may require a minimum frequency greater than dc for proper operation; s ee appropriate table for this information. 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset.
MC68HC908QY4SM/d condensed electrical characteristics mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola condensed electr ical characteristics 47 3-volt oscillator characteristics figure 52. rc versus frequency (3 volts @ 25c) typical supply currents figure 53. typical operating i dd , with all modules turned on (25c) characteristic symbol min typ max unit internal oscillator frequency f intclk ?12.8?mhz crystal frequency, xtalclk f oscxclk 1?16mhz rc oscillator frequency, rcclk f rcclk 2?12mhz external clock reference frequency (1) f oscxclk dc ? 16 mhz 1. no more than 10% duty cycle deviation from 50% 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ; 0 ? ? ? ? 5 5 0 0 ?
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 48 condensed electrical characteristics motorola figure 54. typical wait mode i dd , with adc turned on (25c) analog-to-digital converter characteristics 0 0.25 0.5 0.75 1 1.25 1.50 1.75 2 01 23 456 78 5.5 v 3.3 v i dd (ma) f op or f bus (mhz) characteristic symbol min max unit comments supply voltage v ddad 2.7 (v dd min.) 5.5 (v dd max.) v? input voltages v adin v ss v dd v? resolution b ad 88bits ? absolute accuracy a ad 0.5 1.5 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t adic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v? power-up time t adpu 16 ? t adic cycles t adic = 1/f adic conversion time t adc 16 17 t adic cycles t adic = 1/f adic sample time (1) t ads 5? t adic cycles t adic = 1/f adic zero input reading (2) z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? 8 pf not tested input leakage (3) ?? 1 a? 1. source impedances greater than 10 k ? may adversely affect internal rc charging time during input sampling. 2. zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. the external system error caused by input leakage current is approximately equal to the product of r source and input current.
MC68HC908QY4SM/d condensed electrical characteristics mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola condensed electr ical characteristics 49 memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) 08mhz flash page erase time <1 k cycles <10 k cycles t erase (2) 1 4 ? ? ms flash mass erase time t merase (3) 4?ms flash pgm/erase to hven set up time t nvs 10 ? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 5? s flash program time t prog 30 40 s flash return to read time t rcv (4) 1? s flash cumulative program hv period t hv (5) ?4ms flash row erase endurance (6) ? 10 k ? cycles flash row program endurance (7) ? 10 k ? cycles flash data retention time (8) ? 10 ? years 1. f read is defined as the frequency range for which the flash memory can be read. 2. if the page erase time is longer than t erase (min), there is no erase disturb, but it reduces the endurance of the flash memory. 3. if the mass erase time is longer than t merase (min), there is no erase disturb, but it reduces the endurance of the flash memory. 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. 6. the minimum row endurance value specifies each row of the fl ash memory is guaranteed to work for at least this many erase/program cycles. 7. the minimum row endurance value specifies each row of the fl ash memory is guaranteed to work for at least this many erase/program cycles. 8. the flash is guaranteed to retain data over the entire operating te mperature range for at least the minimum time specified.
MC68HC908QY4SM/d data sheet summary mc68hc908 qy/qt family ? rev. 0.1 50 revision history motorola revision history date revision level description page number(s) september, 2002 n/a initial release n/a december, 2002 1.0 table 1. mc order numbers ? added ordering information for 8-pin dual flat no lead (dfn) package. 1 features ? added 8-pin dfn package. 3 figure 2. mcu pin assignments ? figure updated to include dfn packages. 5 figure 3. memory map ? clarified illegal addr ess and unimplemented memory. 7 figure 4. control, status, and data registers ? corrected bit definitions for port a data register (pta) and data direction register a (ddra). 8 sim reset status register ? clarified description of ilad bit. 16 figure 32. port a data register (pta) ? corrected bit definition for pta7. 35 figure 33. data direction register a (ddra) ? corrected bit definitions for ddra7 and ddra6. 36 keyboard interrupt module (kbi) ? section reworked to remove reference to auto wakeup module. 38 auto wakeup module (awu) ? added description of awu module. 39 condensed electrical characteristics ? section updated. 44
MC68HC908QY4SM/d revision history mc68hc908qy/qt family ? rev. 0.1 data sheet summary motorola revision history 51
MC68HC908QY4SM/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 MC68HC908QY4SM/d rev. 0.1 12/2002

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